1. Field of the Invention
The invention relates to detecting the type of memory devices installed in a computer system, and more particularly to a detection algorithm which can differentiate extended data output memory devices from fast page mode memory devices.
2. Description of the Related Art
Computer systems are becoming ever more powerful by the day. Users are requiring more capabilities to run ever more complicated and sophisticated applications and computer system manufacturers are responding. Computer speeds have dramatically increased over the last number of years so that now desktop and file server computers can readily outperform mainframe computers of 10-15 years ago. But the quest for further performance is never ending. To this end, the microprocessor manufacturers have been developing ever faster microprocessors.
However, a computer system is far more than just a microprocessor. There are many other subsystems that must cooperate with the microprocessor to provide a complete computer system. It is desirable to optimize as many of these subsystems as possible and yet take into account cost and system flexibility to satisfy varied user desires.
Two of the subsystems which have not maintained pace with the development of microprocessor are the main memory systems and the input/output buses. Main memory system shortcomings have been much alleviated by the use of cache memory systems, but in the end all memory operations must ultimately come from the main memory, so that its performance is still a key piece in the overall performance of the computer system. Many advanced memory architectures and techniques have developed over the years. One of the most common techniques is the use of paged mode memory devices or dynamic random access memories (DRAMS), where the actual memory address location value is divided into rows and columns, and if the row address, i.e., the page, is the same for the subsequent operation, only the column address needs to be provided to the DRAM. Although there is a certain amount of overhead required, it easily pays for itself by the improved performance gained during a page hit. So basic page mode operation provides a major performance increase, but more performance is always desired.
One further performance increase relates to an improvement for determining the level of the row address strobe or RAS* signal when the memory system is idle. As is well known, the RAS* signal must be negated, or set high, to allow a new page or row address to be provided and there is also a precharge time requirement. Thus, there is a performance penalty if the RAS* signal is raised when the next operation is actually a page hit. Similarly, there is a delay if the RAS* signal is kept low and the operation is a page miss, as the full precharge time must also be expended after the cycle has been issued. To address this concern, various techniques have been developed to predict whether the RAS* signal should be kept low or should be returned high to indicate a new page cycle. The prediction can be done several ways, as indicated in Ser. No. 08/034,104 filed Mar. 22, 1993, entitled "Memory Controller That Dynamically Predicts Page Misses." In that application several techniques are used. A first technique bases the prediction on the type of the last cycle performed by the processor, with the choice always fixed. A second technique samples the hits and misses for each cycle type and then sets the RAS* level based on this adaptive measurement.
Further, personal computer systems are becoming mass market products, and therefore need to be very flexible to meet the widely varying particular goals of users. For example, some users may desire the ultimate in performance with little regard for cost, whereas other users may be significantly more cost sensitive. One area where cost directly impacts performance is in the type of the memory devices used in the main memory.
For many years, fast page mode (FPM) DRAMs have dominated the memory market. Recently, a new type of DRAM called extended data output (EDO) DRAM has become available. The EDO DRAMs have performance improvements over conventional FPM DRAMs which make their use desirable. A distinguishing characteristic of EDO DRAMs is that during a read cycle, the EDO DRAMs provide data output even after the CAS* signals are deasserted. In this way, a CAS* precharge cycle can be performed in parallel with a read cycle, thereby reducing the overall read cycle time. By contrast, in FPM DRAMs, the data outputs of the DRAMs are tri-stated when the CAS* signals are deasserted, or pulled high.
Systems today are being designed to work with both EDO and FPM DRAMs. However, EDO and FPM DRAMs have different timing requirements. It is known that improper use of the DRAMs can cause premature failure. Thus, problems can develop if the DRAMs are installed improperly into a computer system. Users are oftentimes unaware of the subtle differences between EDO and FPM DRAMs, or are unable to identify the type of DRAM. Furthermore, with the computer becoming more user friendly, it is unreasonable to require users to properly configure memory devices. Therefore, it is desirable to automatically detect the type of DRAM present in the computer system.